//2025-4-22

//二选一逻辑设计

`timescale  1ns/100ps

module fn_sw(a,b,sel,y);

input a;
input b;
input sel;
output y;

//sel为1时 y为a和b的异或 sel为0时， y为a和b的与
// assign y = sel ? (a^b) : (a&b);

//也可以使用always语句来实现
reg y;

always@(a or b or sel) //括号中是敏感变量
begin
    if(sel==1) begin
        y <= a^b;
    end
    else begin
        y <= a&b;
    end

end

endmodule


//testbench of fn_Sw

module fn_sw_tb;
reg a,b,sel;
wire y;

fn_sw fn_sw(.a(a), .b(b), .sel(sel), .y(y));

initial begin
    a <=0; b <=0; sel <=0;
#10 a <=0; b <=0; sel <=1;
#10 a <=0; b <=1; sel <=0;
#10 a <=0; b <=1; sel <=1;
#10 a <=1; b <=0; sel <=0;
#10 a <=1; b <=0; sel <=1;
#10 a <=1; b <=1; sel <=0;
#10 a <=1; b <=1; sel <=1;
#10 $stop;
end

endmodule